`timescale 1ns/1ns
module test_top();

reg clk_50M;
initial clk_50M = 0;
always begin
  #2 clk_50M = ~clk_50M;
end

reg ready, mode;
reg [7:0] devaddr, subaddr1, subaddr2, data_in;
wire tran_done;
wire [7:0] data_out;
wire scl, sda, rst_n;
reset rst(.clk(clk_50M), .rst_n(rst_n));

i2c_tran u1(
  .clk_50M(clk_50M), .rst_n(rst_n),
  .data_valid(ready), .mode(mode),
  .devaddr(devaddr), .subaddr1(subaddr1), .subaddr2(subaddr2), .data_in(data_in),
  .tran_done(tran_done), .data_out(data_out), 
  .scl(scl), .sda(sda),
  .ack_r(ack_r));

EEPROM_AT24C64 eeprom(.scl(scl), .sda(sda));
initial begin
  ready = 0;
  #100;
  #100;
  // prepare data
  // 1. write data 8'h31 to AE_00_00
  mode = 0; 
  devaddr = 8'hAE;
  subaddr1 = 8'h00;
  subaddr2 = 8'h00;
  data_in = 8'h31;
  #200 ready = 1;
  #5000 ready = 0;

  #160000; // waiting

  // 2. write data 8'h13 to AE_00_01
  mode = 0;
  devaddr = 8'hAE;
  subaddr1 = 8'h00;
  subaddr2 = 8'h01;
  data_in = 8'h13;
  #200 ready = 1;
  #5000 ready = 0;

  #160000; // waiting

  // 3. read data from to AE_00_00
  mode = 1;
  devaddr = 8'hAE;
  subaddr1 = 8'h00;
  subaddr2 = 8'h00;
  data_in = 8'h00;
  #200 ready = 1;
  #5000 ready = 0;

  #160000; // waiting

  // 4. read data from to AE_00_01
  mode = 1;
  devaddr = 8'hAE;
  subaddr1 = 8'h00;
  subaddr2 = 8'h01;
  data_in = 8'h00;
  #200 ready = 1;
  #5000 ready = 0;

  #160000; // waiting

  // 5. clear state and end test
  #200;
  mode = 0;
  devaddr = 8'h00;
  subaddr1 = 8'h00;
  subaddr2 = 8'h00;
  data_in = 8'h00;
  $stop;
end


endmodule